The project EURIPIDES — conceiving, reusing and prototyping, EURopean Intellectual Property In Designing Electronic Systems — aims at providing specialized designs and design tools, resulting in design methodologies, for alleviating the construction of complex systems in key application domains. EURIPIDES conforms to one of the paramount aims of MEDEA, which is to maintain the leading edge that Europe possesses in the fields of telecommunications, automotive and multimedia technologies. In this context, the protection, creation and reuse of the european intellectual property is a matter of primary importance.

Today, large and complex designs are accomplished in a tedious manner by using a variety of commercial and point tools along with the needed software patches. Such sizes and complexities of designs have been empowered by the vast strides taken in the manufacturing technology of integrated circuits. The primary factors in keeping pace with the technology is to increase the overall design productivity and to reduce the time to market, by orders of magnitude. However, there is already a capacious gap between what can be put into silicon and the capabilities of the CAD tools. This gap is going to widen further, and in our opinion there are two pivotal solutions to combat this problem. Firstly, design reuse and migration to higher levels of abstraction will augment the productivity and secondly prototyping will decrement the time to market. Design reuse is nevertheless closely related to the intellectual property issues. Additionally, the shift towards the higher levels of abstractions is coupled with two difficulties in safeguarding the intellectual properties of the system houses:

  • if european system houses continue to rely on purely non-european CAD tools, problems are bound to occur, since the product information is totally exposed, and
  • in contrast to the lower levels of abstraction, copious amounts of application dependent information is required to build the most optimal design tools for a particular application.
  • Towards circumventing the intricacies of designing systems in the mentioned application domains, we shall adopt a two-pronged approach in EURIPIDES. On the one hand, actual designs such as, a configurable correlation chip for mobile telecommunications, video-conferencing (multimedia) support chips e.g. ATM chips (automotive) will be produced. These designs will act as the guiding beacon in driving the design tools that will also emanate from EURIPIDES. The major impetus in advancing the design tools will be made possible by focusing our efforts in two new areas namely, design reuse and HW/SW prototyping and verification. In the area of design reuse two complementary approaches will be explored — reusing existing designs and design for reusability. The latter area is motivated by the enormous reductions in the time to market that can be achieved via the early introduction of prototyping and verification techniques. Special emphasis will also be laid on designing for low power consumption, starting at higher levels of abstraction, due to nature of the application domains.

    List of Partners

    Bull S.A., Les Clayes-sous-Bois (France) Forschungszentrum Informatik, Karlsruhe (Germany)
    TU Chemnitz (Germany) Fraunhofer-Institut EAS, Dresden (Germany)
    INPG/CSI, Grenoble (France) OFFIS, Oldenburg (Germany)
    Philips Research, Eindhoven (The Netherlands) Quickturn Design Systems, München (Germany)
    Robert Bosch GmbH, Reutlingen (Germany) SGS-Thomson, Grenoble (France)
    Siemens AG, München (Germany) Synopsys GmbH, München (Germany)
    Thomson-CSF Communications, Gennevilliers (France) Thomson-CSF Semiconducteurs Spécifiques, Saint-Egrève (France)
    Design & Reuse, Grenoble (France)

    © Ralf Seepold, FZI Karlsruhe, 1998,1999, 2000